The present invention relates in general to the field of integrated circuit packages and more specifically to substantially flat integrated circuit packages having high solder joint stress reliability.
Semiconductor integrated circuit chips have to be assembled in order to enable them to interact electrically with the outside world. For this reason, chips are mechanically positioned on supports and electrically connected for power, ground and signal lines. For stable mechanical positioning, chips are commonly attached (for example by glueing or soldering) to metallic, glassy or polymer substrates. For permanent electrical connection, chips are bonded by whisker wires or solder balls to conductors leading to outside electrical circuitry. In order to protect the sensitive whisker wires mechanically and to shield the chip against environmental disturbances, the assembled chip is commonly encapsulated in polymer or molding material, or housed in a ceramic package.
As a result, these semiconductor assemblies contain materials with different coefficients of thermal expansion (CTE); they are often coupled mechanically intimately, even rigidly to each other. Expressing CTE in ppm/xc2x0 C., silicon has approximately 2.3, various metals from 4.3 to 17.0, and various plastics from 16.0 to 25.0. Consequently, whenever these assemblies undergo temperature excursions, the swings of increasing and decreasing temperatures induce different expansions and contractions in the materials coupled to each other, causing tensile and compressive stresses to build up in the component parts. If the package were a uniform laminate structure, the stresses in each individual layer could be analytically modeled. However, the package is not a uniform laminate, and the variations from the inuform laminate case create stress concentrations. Further, the package is assembled through a series of thermal process steps which build in stresses between various layers. Finite element analysis and measurements by test structures have proven useful in quantifying these stresses.
For plastic encapsulated silicon chips, adhered to metallic leadframes by polymer adhesives, these stresses were first analyzed in 1984 (Ref. 1: xe2x80x9cComputer-aided Stress Modeling for Optimizing Plastic Package Reliabilityxe2x80x9d, by S. Groothuis, W. Schroen and M. Murtuza, 23rd Ann. Proc. Int. Reliab. Phys. Symp, pp. 184-191, 1985; Ref. 2: xe2x80x9cPlastic Packagingxe2x80x9d by W. Schroen, IRPS Tutorials 1985, pp. 4.1-4.18) and showed that shear stresses exhibit steep maxima when they are measured from the center of the chip towards the corners. Taken from Ref. 2, FIG. 1 shows the shear stress immediately above the chip, with the shear stress parallel to the surface of the chip reaching an intense maximum at each corner and approaching zero at the chip center. Quantitative strain values were obtained using diffused strain gauges integral with the silicon chip. With the additional effect of compressive stress in thermal cycling (for example, from xe2x88x9265 to +150xc2x0 C.), the chip undergoes a pillow-shaped distortion.
Frequently, these strain and stress maxima were seen to cause severe reliability failures of the devices investigated. For instance, cracks in plastic materials close to the chip corners (especially adhesives and molding material) were observed; passivation layers over the silicon developed cracks; metallization lines in the corners of the integrated circuit shifted; gold wires ball-bonded close to the corners were ripped out of their chip bonding pads.
In the following years, those original observations have been confirmed numerous times and for many different semiconductor packages (for instance Ref. 3: xe2x80x9cVLSI Packaging Thermomechanical Stressesxe2x80x9d by D. Edwards, S. Groothuis, and M. Murtuza, IRPS Tutorials 1988, pp. 8.1-8.39). For devices encapsulated in the conventional dual-in-line and quad-flat packages, the industry has learned in the late 1980""s and early 1990""s, to mitigate or bypass many of these stress effects through careful circuit layout rules and proper choice of the materials. However, with the recent emergence of plastic ball-grid array packages, serious reliability risks from stress effects reappeared. Recently, measurements on semiconductor packages of the ball-grid array (BGA) type and chips-size (CSP) type found that the solder joints located close to the package corners (and close to the chip corners for flip-chip devices) are under particularly heavy strain. Using the universal relationship by Coffin and Manson, which relates the number of temperature cycles leading to failure of the solder joint with the strain induced per cycle, reasearchers were able to predict the number of temperature cycles needed to initiate failure. Using this analytical equation and empirical and geometric constants for the solder material employed, the lifetime in temperature cycling (for example, from 0xc2x0 C. to +100xc2x0 C.) could be predicted. It turned out to be shortest (for example, less than 2000) for the solder joints close to the package and chip corners.
A number of approaches have been proposed to mitigate the level of internal mechanical stress. For example, Christie et al. (U.S. Pat. No. 5,250,848 of Oct. 5, 1993) have disclosed the use of certain encapsulants to absorb part of the internal stress. Melton et al. (U.S. Pat. No. 5,233,504 of Aug. 3, 1993) and Okumura (U.S. Pat. No. 4,807,021 of Feb. 21, 1989) use balls made of materials of relatively high melting temperatures that have been coated with a layer of soft material. During package assembly, the balls do not melt so a collapse, due to weight, into a barrel shape with its significant built-in stress does not occur. After assembly, the soft outer layer acts as a buffer to absorb some of the built-in or subsequently generated stress. Blanton (U.S. Pat. No. 5,220,200 of Jun. 15, 1993) prevents the solder ball collapse with its highly stressed barrel shaped solder joints by providing pillers that support the ball gris array during melting. These pillera are made of a metal paste laid down by several paste screening processes. Ho (U.S. Pat. No. 5,598,036 of Jan. 28, 1997) uses two sets of solder joints that have different melting points. The joints with the higher melting point are positioned in the region, on the ball grid array, where it is known that stress will be a maximum in the finished package. The joints with lower melting solder occupy the remaining positions on the underside of the ball grid array.
While some of these proposals resulted in modest improvements, none of them attacked the essential failure mechanism, which is always the failure of the weakest joint. Consequently, a need has arisen for a more fundamental solution to the failure mechanism of the weakest link, as well as methods to fabricate devices using low-cost processes. The improved reliability should be achieved without jeopardizing the stringent requirements of low-profile ball-grid array and small-outline packages. Preferably, these improvements should be accomplished using the installed equipment base so that no investment in new manufacturing machines is needed.
The present invention comprises semiconductor ball-grid array packages, chip-size packages and flip-chip assemblies with improved mechanical reliability achieved by electrical redundancy of input/output terminals. The invention defines the design rules for the electrical redundancy and the methods for fabricating the chip inputs/outputs and the solder ball configuration of BGA packages.
The present invention applies certain results taken from mathematical probability and failure theory. In assessing the failure of the solder joints of an assembled flip-chip device, BGA package, or chip-size package, the two-dimensional array of solder joints is conceptually equivalent to a long xe2x80x9cchainxe2x80x9d of structurally and statistically independent members, arranged sequentially. Consequently, it is important to notice that the chain fails, when the weakest member fails.
In contrast to the failure mode of a chain is the failure mode of a xe2x80x9cbundlexe2x80x9d consisting of members arranged in parallel with no bonding or friction between the members. If one or even several of the members have failed, the bundle as a whole has not yet failed, but rather all non-failed members share the bundle strength. Consequently, the strength of the bundle is higher than the minimum strength of the individual members; how much higher, depends on the individual values with the rank position of the individual member within the bundle (it may even approach the value of the maximum individual member strength). It follows that by operating a bundle in parallel mode, its strength is significantly enhanced, the risk of total failure is much reduced, and thus the reliability is improved.
For the invention, the xe2x80x9cbundlexe2x80x9d consists of the number of solder joints operating in parallel to serve one terminal of the device (in the high-strain regions of the device). xe2x80x9cServing one terminalxe2x80x9d is equivalent to xe2x80x9celectrically redundantxe2x80x9d. According to the invention, when the reliability of a semiconductor device is expressed by the number of temperature cycles it can survive before failure, then this number of cycles increases dramatically with the number of electrically redundant solder joints in the high-strain regions of the device. In order to meet the reliability typically expected of semiconductor products inspite of the stresses observed in the high-strain regions in many BGA and CSP device types, the number of needed electrically redundant solder joints varies between 2 and 6.
It is an object of the present invention to leapfrog to the order-of-magnitude higher reliability of the next generation of semiconductor product in ball-grid array and chip-size packages by selective and optimized electrically redundant solder joints.
Another object of the present invention is to provide reliability assurance for the finished product by changing the failure mechanism from a probabilistic weakest-link mode to a parallel-type mode, effectively eliminating the failure mechanism.
Another object of the present invention is to provide a design method of electrical redundancy which are flexible so that they can be applied to several families of products, and are general, so that they can be applied to several future generations of products.
Another object of the present invention is to provide a low-cost process for fabrication and assembly.
Another object of the present invention is to minimize the cost of capital investment and to use the installed fabrication equipment base.
These objects have been achieved by the design of the chip and the package of the invention and a mass production process. Various modifications have been successfully employed for electrical redundancy of the packages and the assembly of individual packages and packages-on-board.
In one embodiment of the invention, the selection rules for electrical redundancy are described in relation to the chip terminals in the high-stress areas of the chip, creating contact pads in parallel and operated redundantly.
In another embodiment of the invention, solder balls are disposed on the chip contact pads and assemblies produced using flip-chip technology.
In a further embodiment of the invention, ball-grid array and chip-size packages are selected to determine the minimum number of redundancy needed to meet the required reliability criterion for the selected package.
In another embodiment of the invention, ball-grid array and chip-size packages, designed with parallel terminals, are used to operate few I/O solder balls in parallel to highlight that from a statistical point of view the parallel operation, like a fiber-reinforced composite, is more reliable than the chain-operated monolithic counterpart.
The technical advances represented by the invention, as well as the objects thereof, will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.